The present invention generally relates to a method for conducting backside failure analysis on a wafer that requires simple bias conditions and a wafer specimen for conducting such analysis and more particularly, relates to a method for conducting backside failure analysis on a wafer that requires simple bias conditions by adhering metal foils to the surface of the wafer and connecting by wire bonding to bond pads on the wafer surface for feeding a bias voltage to a defective IC die and observing a defect from the backside of the wafer and a wafer test specimen for conducting such backside failure analysis.
In the semiconductor fabrication technology, the capability and effectiveness of performing a failure analysis on a semiconductor chip package are very important. When an integrated circuit (IC) chip fails in service, the nature and the cause for such failure must be determined in order to prevent the reoccurrence of such failure in similar products.
An IC chip is normally built on a silicon base substrate with many layers of insulating materials and metal interconnections. This type of multi-layer structure becomes more important in modem IC devices such as high density memory chips where, in order to save chip real estate, the active device is built upwards in many layers forming transistors, capacitors and other logic components.
When an IC device is found defective during a quality control test, various failure analysis techniques can be used to determine the cause of such failure. Two of the more recently developed techniques for performing failure analysis are the infrared light emission microscopy and the light-induced voltage alteration (LIVA) imaging technique. In the infrared light emission light analysis, an infrared light transmitted through a substrate silicon material is used to observe from the backside of an IC the failure mode of the circuit. For instance, at a magnification ratio of 100x, a failure point in the circuitry can be located. The LIVA imaging technique can be used to locate open-circuited and damaged junctions and to image transistor logic states. The LIVA images are produced by monitoring the voltage fluctuation of a constant current power supply when a laser beam is scanned over an IC. A high selectivity for locating defects is possible with the LIVA technique.
Another method that has become more common in failure analysis of IC chips is the scanning optical microscopy (SOM). The high focusing capability of SOM provides improved image resolution and depth comparable to conventional optical microscopy. It is a useful tool based on the laser beam""s interaction with the IC. The SOM technique enables the localization of photocurrents to produce optical beam induced current image that show junction regions and transistor logic states. Several major benefits are made possible by the SOM method when compared to a conventional scanning electron microscopy analysis. For instance, the benefits include the relative ease of making IC electrical connection, the no longer required vacuum system and the absence of ionizing radiation effects.
Even though the above discussed techniques arc effective in identifying failure modes in IC circuits, the techniques require elaborate and complicated electronic equipment which are generally costly and not readily available in a semiconductor fabrication facility. It is therefore desirable to have available a method and apparatus that can be easily carried out without expensive laboratory equipment such that the apparatus can be installed in any fabrication facilities. One such apparatus utilizes a liquid crystal coating layer for the identification of failure sites in an IC chip. For instance, in the method wherein a liquid crystal layer is used for the identification of failure sites, a liquid crystal material is frequently coated on top of an IC chip or an IC package. A typical test set up is shown in FIG. 1.
As shown in FIG. 1, a typical liquid crystal detection apparatus 10 is provided. The apparatus 10 generally includes a heater 12 and an optical microscope 14. On a top surface 16 of the heater 12, an IC package 20 is positioned under the microscope 14. The IC package 20 may be a plastic quad flat pack (PQFP) or any other packaged IC device. The IC package 20, shown in FIG. 1, is completed with bonding pads 22 and bonding wires 24. In the middle portion of the package 20 are IC circuits that contain failure sites need to be identified by a liquid crystal method. In the conventional method, a liquid crystal material is first coated to the top surface 26 of the IC package 20. The IC package 20 is then positioned on top of the heater 12 which can be heated at a pre-programmed heating rate to a specific temperature. The IC package 20, together with the coated liquid crystal layer (not shown) is normally heated to a temperature just below the clear/opaque transition temperature of the liquid crystal material. For instance, a suitable temperature would be approximately between about 5xc2x0 and about 10xc2x0 below the transition temperature of the liquid crystal. After the IC package 20 is heated to the predetermined temperature, a pre-selected voltage is applied to the IC circuit through bonding wires 24. The IC circuit, upon receiving such a voltage, heats up at any short or leakage positions. A hot spot is thus generated at each of the locations. The liquid crystal material immediately adjacent, or contacting the hot spots has its temperature raised above its transition temperature and transforms from an opaque state to a clear state. As a result, bright spots in the liquid crystal layer, i.e., on the IC package, show up to indicate the failure sites in the package.
Several drawbacks have been noted in the practice of the liquid crystal detection method. One of the obvious drawbacks is that when testing IC chips of different sizes, a single test board cannot be used for all IC chips. A different test board is required for testing chips of different sizes such that the chip can be mounted on the board for making electrical connections by wire bonding with the conductive leads provided on the test board. Based on the large number of IC chips of different sizes it is a tedious task to supply a large number of test boards that will fit each individual chip. Ideally, a universal test board should be designed such that it will fit different sizes of IC chips for testing.
Regardless which one of the failure analysis techniques is adopted, an IC chip package must be properly prepared with a suitable surface for performing a failure analysis. Since most modem IC chips utilizes at least two or more layers of metal thin films as interconnect layers, the active components of the chip on which the failure analysis is to be performed are usually shielded by the metal interconnect layers. Great difficulties are encountered in performing any of the failure analysis techniques, i.e., the infrared light emission microscopy, the LIVA imaging technique or the SOM technique, which cannot penetrate the layers of metals to detect the failure mode in the circuit.
In another more recently developed package for IC chips, i.e., the lead-on-chip (LOC) package, both the lead frame and the bounding wires are positioned on top of an IC circuit. The LOC package has been used in modem high density memory devices wherein a plurality of finger leads are disposed on and attached to an active surface of an IC chip. The benefits of using a LOC package is that the ratio between the size of an IC chip and the size of a package (which encapsulates the chip) is significantly higher than conventional packages since the mounting area (die pad) is no longer required in a LOC package. A high ratio between the chip size and the package size is very desirable in the ever increasing miniaturization of IC devices. A metal lead frame is normally used in a LOC package which substantially covers the active device.
Attempts have been made by others to perform failure analysis on the back surface of an IC chip package. For instance, the back surface of an IC chip package can be polished away to remove the encapsulating material and to expose the die back. A typical backside failure analysis conducted on an IC chip in an emission microscope is shown in FIG. 2. An emission microscope is an instrument that provides the location of localized light emissions in a field. The instrument is normally used for observing visible light emitted from voltage biased faulty semiconductor devices without the need for studying semiconductor materials directly. In order to examine the spectra distribution of the localized emissions and to determine the type of defects most likely caused the emission, a series of narrow band optical filters may be utilized in the light path of the microscope. The emission microscope is useful in studying the backside of an IC chip that is formed with multiple layers of conducting metals, such as in a transistor that is arranged under the multiple layers. In such a structure, it is difficult to detect emission from the front surface of the device and thus, necessitates the technique of backside failure analysis as shown in FIG. 2. By using an infrared light transmitted through the silicon layer of the IC device (which is transparent to IR), an observation from the backside of the IC is possible for failure site identification.
A problem in the test method shown in FIG. 2 is that the lead frame connecting the IC circuit can be easily damaged during the polishing process. A damaged lead frame cannot be electrically connected by soldering to a printed circuit board or by clamping to a test socket. As a consequence, a bias voltage which is required for performing the failure analysis cannot be applied to the circuit. The problem of making an electrical connection to the circuit to be tested therefore renders the performance of a failure analysis impossible.
It is therefore an object of the present invention to provide a method for backside failure analysis that requires simple bias conditions without the drawbacks or shortcomings of the conventional backside failure analysis methods.
It is another object of die present invention to provide a method for backside failure analysis that requires simple bias conditions that can be executed on the wafer scale without severing into individual dies.
It is a further object of the present invention to provide a method for backside failure analysis that requires simple bias conditions that can be used to analyze defective IC dies on a wafer without damaging other good dies.
It is another further object of the present invention to provide a method for backside failure analysis that requires simple bias conditions that does not require packaging steps to be performed in order to make electrical connections to the defective IC dies.
It is still another object of the present invention to provide a method for backside failure analysis that requires simple bias conditions by adhesively bonding conductive metal foils to the surface of the wafer and then wire bonding the foils to the bond pads on the defective IC die for feeding a bias voltage thereto.
It is yet another object of the present invention to provide a method for backside failure analysis that requires simple bias conditions that utilizes metal foils and wire bonds for feeding a bias voltage to a defective IC die and observing the defect from the backside of the wafer by infrared CCD.
It is still another further object of the present invention to provide a wafer sample for observing defects from a bottom surface of the wafer which includes at least two conductive metal strips adhesively bonded to the top surface of the wafer and at least two lead wires providing electrical communication between the conductive metal strips and bond pads on die defective IC die.
It is yet another further object of the present invention to provide a wafer specimen for observing defects from a backside of the wafer which includes a wafer that has at least one defective IC die in an active surface, at least two conductive strips made of metal foils adhesively bonded to the active surface of the wafer juxtaposed to the at least one defective IC die, and at least two lead wires electrically connecting the at least two conductive strips to the bond pads on the at least one defective IC die to provide a bias voltage to the die such that defects in the die can be observed in the wafer backside under IR CCD.
The present invention discloses a method for conducting backside failure analysis on a wafer that requires simple bias conditions and a wafer test specimen that can be analyzed by such method.
In a preferred embodiment, a method for conducting backside failure analysis on a wafer that requires simple bias conditions is provided which includes the steps of providing a wafer that has at least one defective IC die in an active surface, adhesively bonding at least two conductive metal strips on the active surface juxtaposed to the at least one defective IC die, wire bonding at least two lead wires for establishing electrical communication between the at least two conductive metal strips and the at least two bond pads, respectively, supplying a bias voltage to the at least one defective IC die through the at least two conductive metal strips, and observing a bottom side of the wafer for defects.
The method for conducting backside failure analysis on a wafer that requires simple bias conditions may further include the step of providing at least two conductive metal strips in metal foils of Al or Cu. The method may further include the step of providing the at least two lead wires in Au. The method may further include the step of providing the at least two lead wires in a length not longer than 15 mm, or in a length between about 5 mm and about 15 mm. The method may further include the step of adhesively bonding four conductive metal strips on the active surface with two strips each on the opposite sides of the at least one defective IC die.
The method for conducting backside failure analysis on a wafer that only requires simple bias conditions can be further executed by the additional step of supplying the at least two conductive metal strips in metal foils coated with an adhesive backing, the step of providing the at least two conductive metal strips in a width smaller than 5 mm. The method may further include the step of supplying a bias voltage for VCC or for clock signals. The method may further include the step of observing the wafer backside by an IR CCD. The method may further include the step of turning the wafer upside down and positioning the wafer on a sample holder.
The present invention is further directed to a wafer specimen for observing defects from a bottom surface of the wafer that includes a wafer that has at least one defective IC die in a top surface, at least two conductive metal strips adhesively bonded to the top surface of the wafer parallel to one side of the at least one defective IC die, and at least two lead wires providing electrical communication between the at least two conductive metal strips and a corresponding bond pad on the at least one defective IC die and for providing a bias voltage to the die such that defects in the die may be observed in a bottom surface.
In the wafer specimen for observing defects from a bottom surface of the wafer, the at least two lead wires arc bonded to the at least two conductive metals and the corresponding bond pads by an wire bonding process. The at least two conductive metal strips are formed of metal foils of Al or Cu, the metal foils may have a width smaller than 5 mm. The at least two lead wires may have a length of not longer than 15 mm. The at least two conductive metal strips are metal foils coated with an adhesive backing. The wafer specimen may further include four conductive metal strips adhesively bonded to the top surface of the wafer parallel to two opposing sides of the at least one defective IC die.
In another preferred embodiment, the present invention provides a method for conducting failure analysis on a wafer backside that only requires simple bias conditions to be fed into at least one defective IC die which can be executed by the steps of first providing a wafer that has at least one defective IC die in a top surface, then bonding at least two adhesive backed conductive metal foils on the top surface juxtaposed to the at least one defective IC die, bonding at least two lead wires not longer than 15 mm for establishing electrical communication between the at least two conductive metal strips and the at least two bond pads in the active surface, respectively, feeding a bias voltage to the at least one defective IC die through the at last two conductive metal foils, turning the wafer upside down and positioning on a sample holder, and observing a bottom side of the wafer for defects by an optical detector. The method may further include the step of feeding the bias voltage of VCC or clock signals.